D.C.-d.c. converter with a transformer and a reactance coil

ABSTRACT

A DC-DC converter having a transformer, a reactance coil and a controllable switch for turning a DC supply voltage on and off. The contact gap of a switching transistor is set at a reference potential at a connecting tap between a primary winding and a secondary winding of the reactance coil, which is connected like a transformer with a certain transformation ratio. The anode-cathode segment of a diode and an output capacitor are set at reference potentials in series with the secondary winding of the reactance coil, with the output voltage for a load being applied across the output capacitor. The DC supply voltage is supplied to the primary winding of the reactance coil over an inductance arrangement, and a capacitance arrangement is arranged in parallel with the contact gap of the switching transistor so that a series resonant circuit, which is operative in the turn-on and turn-off phases of the switching transistor, is provided by the inductance arrangement and the capacitance arrangement.

BACKGROUND INFORMATION

1. Field of the Invention

The present invention relates to a DC-DC converter having a transformerand a reactance coil and a controllable switch for turning the DCvoltage supply on and off definition of the in claim 1.

2. Background Information

To supply power to loads, DC-DC converters in various designs are usedfor many purposes, e.g., for supplying power to gas discharge lamps, inparticular high pressure gas discharge lamps used in motor vehicles.

Thus, for example, flyback converters, flux converters and CuKconverters may be used. In addition, quasi-resonant converters arediscussed in “Quasi-Resonant Converters Topologies and Characteristics”by Kwang-Hwa Liu, Ramesh Oruganti and Fred Lee: IEEE Transactions onPower Electronics, vol. PE-2, no. 1, Jan. 1987.

SUMMARY OF THE INVENTION

An object of an exemplary embodiment of the present invention is toprovide a DC-DC converter that provides a voltage transformer having ahigh efficiency at the lowest possible cost through circuit technologymeasures.

The DC-DC converter according to an exemplary embodiment of the presentinvention is believed to provide a considerable reduction in switchinglosses at what is believed to be very low cost in terms of the circuittechnology. Another special advantage is the reduced EMP(electromagnetic pollution) and the associated phenomena andcountermeasures.

According to an exemplary embodiment of the present invention, the inthe DC-DC converter, which is designed as a constant-currenttransformer, is that the contact gap of a switching transistor is set atthe reference potential at the connecting tap between the primary andsecondary windings of the reactance coil which is connected as atransformer with a certain transformation ratio; the anode-cathodesegment of a diode and an output condenser are arranged at the referencepotential in series with the secondary winding of the reactance coil,where the output voltage for a load is supplied over the outputcapacitor; the input DC voltage is sent to the primary winding of thereactance coil via the reactance coil, and a capacitor is arranged inparallel with the contact gap of the switching transistor, thus creatingwith the inductance and the capacitance a series resonant circuit thatis effective in the turn-on and turn-off phases of the switchingtransistor.

According to an other exemplary embodiment of the voltage transformeraccording to the present invention, the switching transistor is switchedto conducting when the voltage applied to its conducting segment isapproximately at a value of zero. In another exemplary embodiment, acircuit is provided that detects the voltage applied to the conductingsegment of the switching transistor and detects its zero crossings.Through these measures, conducting state power losses and switchinglosses of the switching transistor are greatly reduced.

In an expedient refinement of this exemplary embodiment of the presentinvention, the switching transistor is a MOS-FET transistor.

According to another exemplary embodiment of the voltage transformeraccording to the present invention, which contributes toward a furtherreduction in cost, the reactance coil upstream from the primary windingis implemented as a discrete reactance coil or, with a suitable choiceof the coupling factor, as the leakage inductance of the reactance coil.

According to another exemplary embodiment of the present invention, thecapacitor to be connected parallel to the contact gap of the switchingtransistor can be implemented by a discrete capacitor or by theparasitic output capacitance of the component or by a combination of thetwo possible embodiments.

In another exemplary embodiment of the present invention, the MOS-FETtransistor is controlled at the gate with a gate resonance control.

According to an exemplary embodiment of the present invention, a gateresonance control or controller is also made available in particular forcontrolling a DC-DC converter such as that provided by the measuresaccording to the exemplary embodiment of the present invention, in whichthe gate resonance control includes a gate reactance coil upstream fromthe gate of a MOS-FET transistor which switches the DC supply voltage,where the gate reactance coil can be connected to a control voltagesource over the cathode-anode segment of a first diode and a firsttransistor switch, but it can also be connected to reference potentialover the anode-cathode segment of a second diode and a second transistorswitch, where the parasitic gate-drain capacitance and the parasiticgate-source capacitance are used as capacitances for the resonantcircuit, and the clock cycle of turning the two transistor switches onand off is selected so that the gate voltage escalates in the desiredmanner. In another embodiment of this gate resonance control, bipolartransistors are used as the transistor switches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a circuit arrangement of the DC-DCconverter according to an exemplary embodiment of the present invention.

FIG. 2 shows a diagram with the variation over time of various signalswith a “traditional” voltage transformer.

FIG. 3 shows a diagram with the variation over time of various signalsin the circuit arrangement according to an exemplary embodiment of thepresent invention, for comparison with the corresponding signals in FIG.2.

FIG. 4 shows a block diagram of a gate resonance control arrangementaccording to an exemplary embodiment of the present invention.

FIG. 5 shows a time diagram of different signals occurring with theswitching operations of the gate resonance control arrangement.

FIG. 6 shows a block diagram for the circuit arrangement of the DC-DCconverter together with the gate resonance control arrangement accordingto an exemplary embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1 shows schematically in a block diagram the circuit of the DC-DCconverter according to an exemplary embodiment of the present invention,which is referred to below simply as a voltage transformer. A source 1with voltage U_(B) is connected in series with a reactance coil L1 andprimary winding L2P of a reactance coil 2 connected as a transformerhaving a transformation ratio ü to the contact gap of a transistor S1,which may be a MOS-FET transistor. At the tie point of the contact gapof transistor S1 with primary winding L2P, an output capacitor C2 isconnected over a secondary winding L2S of reactance coil 2 and theanode-cathode segment of a diode D1. Output voltage U_(A) is availableat this output capacitor C2 and in conjunction with a current I_(A). Itis also applied to a load resistor R_(L) which is connected in parallelto capacitor C2. A capacitor C1 is arranged in parallel with the contactgap of switching transistor S1. Switching transistor S1 is controlledand switched at its gate by an auxiliary voltage source 3 with voltageU_(H).

The voltage transformer designed as a reactance converter is thuscomposed of switching transistor S1, reactance coil 2 which is connectedas a transformer having transformation ratio ü, diode D1 and outputcapacitor C2.

In the phase in which switching transistor S1 is conducting, magneticenergy is stored in primary reactance coil inductor L2P, the energy thusstored is delivered to the load circuit, i.e., capacitor C2 and loadresistor RL, in the non-conducting phase of switching transistor S1. Thecurrent in the load circuit commutates across diode D1. Transformationratio ü of reactance coil 2 is determined by the ratio of L2P+L2S toL2P.

FIG. 2 shows a diagram of the variation over time of various signals fora traditional voltage transformer. In the diagram at the top, inputcurrent I_(B) is plotted over time t with a phase S11 during whichswitching transistor S1 is conducting, i.e., is switched on, and with aphase S10 during which switching transistor S1 in FIG. 1 isnon-conducting. Current I_(B) increases from zero up to a maximum valueat the switching point, then drops steeply during switching and losstime t_(V) and then drops more gradually to zero. The middle diagramshows voltage U_(S1), plotted over time with a low conducting-statevoltage in phase S11 when switching transistor S1 in FIG. 1 isconducting and with a high voltage in phase S10 when switchingtransistor S1 is non-conducting, i.e., it is turned off. The respectivevoltage transition at the switching time is very steep, almostrectangular.

The lower diagram shows power loss P_(V) plotted over time t. Before theswitching point, there is a slight increase in conducting state powerloss PVDS1 according to the rising current value and the uniformly lowconducting-state voltage; then after the switching point, loss PVSS1occurring during switching time t_(V) increases steeply according to thesteep increase in voltage US1. This is represented by the clearlydiscernible peak in FIG. 2.

As thus shown by the diagram in FIG. 2, power loss P_(V) in switchingtransistor S1 assumes very large values in the transition from theconducting state to the non-conducting state. The efficiency that can beachieved with this traditional voltage transformer is determinedessentially by these turn-off losses.

According to an exemplary embodiment the present invention, reactancecoil L1 and capacitor C1 are introduced as illustrated in the circuitaccording to FIG. 1. Thus, the traditional structure of the voltagetransformer is expanded by the addition of a series resonant circuitwhich is effective in the turn-off and non-conducting phases ofswitching transistor S1. In this way, a quasi-resonant converterstructure is made available.

FIG. 3 shows various signals in the circuit according to an exemplaryembodiment of the present invention in time diagrams in comparison withthe corresponding signals in FIG. 2. Curves for input current I_(B),voltage U_(S1), at switching transistor S1 and power loss P_(V) on thequasi-resonant reactance coil converter are shown.

In the upper diagram, input current I_(B), is plotted over time t with aphase S11 during which switching transistor S1 in FIG. 1 is conducting,i.e., it is turned on, and with a phase S10 during which switchingtransistor S1 in FIG. 1 is non-conducting. Current I_(B) increases fromzero up to a maximum value at the switching point, drops steeply duringswitching and loss time t_(V) and then drops more gradually to zero.

The middle diagram shows voltage U_(S1), plotted over time t with a lowconducting-state voltage in phase S11, when switching transistor S1 inFIG. 1 is conducting and with a sinusoidal voltage rising and falling tozero in phase S10, when switching transistor S1 is non-conducting, i.e.,it is turned off. The respective voltage transition at the switchingtime is very flat due to the sinusoidal form in comparison with thealmost square-wave shape in FIG. 2. The lower diagram shows power lossP_(V) plotted over time t. According to the increasing current value andthe uniformly low conducting-state voltage, there is a slight increasein conducting state power loss PVDS1 before the switching point; thenafter the switching point, loss PVSS1 occurring during switching timet_(V) advantageously drops rapidly to zero in accordance with the rapiddrop in the value of current I_(B), than the value of voltage US1 whichdoes not increase as steeply. This is illustrated with the descendingbranch which is shown clearly in FIG. 3.

The switching operations taking place with the circuit according to FIG.1, which can also be implemented on the basis of the signal curves shownin FIG. 3, are explained below. It should be assumed that switchingtransistor S1 is conducting. It then carries current I_(B), which canalso be referred to as the magnetization current. It is determined byinductances L1 and L2p as well as input voltage U_(B). When switchingtransistor S1 is turned off, the current is commutated into capacitor C1arranged in parallel with the contact gap of switching transistor S1.The current through switching transistor S1 drops to zero very rapidly.Capacitor C1 and reactance coil (L1+L2p) together form a series resonantcircuit which is connected to the positive pole of input voltageU_(B)and to the ground potential. The voltage across switchingtransistor S1 thus increases in a sinusoidal pattern. The turn-off powerloss P_(V) resulting from the transistor current and the voltage acrossthe switching transistor is consequently many times lower than that witha traditional DC-DC converter, as shown by a comparison of the diagramsin FIGS. 2 and 3. The energy stored in capacitor C1 at switch-off timefluctuates in the form of a damped oscillation between the resonantelements. Energy is fed back into voltage source 1, e.g., a battery. Assoon as the voltage on the anode of diode D1 is greater than outputvoltage U_(A), diode D1 becomes conducting. Energy stored in reactancecoil L2p in the conducting phase S11 of switching transistor S1 is fedinto the load circuit. The remaining energy still present in the seriesresonant circuit is also commutated into the load over diode D1. Tominimize turn-on losses at switching transistor S1, switching transistorS1 is switched on according to another exemplary embodiment of thepresent invention when the voltage across it is zero. To do so, acircuit unit is provided to detect the zero crossings and the voltageacross switching transistor S1. This circuit unit is not shown in thefigures.

With regard to the elements of the series resonant circuit, thefollowing can be said. Resonant inductance L1 can be provided as adiscrete coil in the circuit. Through a suitable selection of thecoupling factor of reactance coil 2, however, inductance L1 can also beimplemented through the leakage inductance of reactance coil 2 and fedinto the voltage transformer. This eliminates the need for a separatecomponent.

When using a MOS-FET transistor as switching transistor S1, resonantcapacitance C1 can be implemented through the parasitic outputcapacitance of this component. However, since this output capacitancehas a great deal of leakage, depending on the voltage across thetransistor, it may then be expedient to provide a discrete capacitor inparallel with the output capacitance. The tolerance range of thecapacitance is narrower due to the use of the discrete capacitor.

The conducted disturbance which is emitted through the air and alwaysoccurs in “hard” switching is minimized through the “soft” turn-on andturn-off of switching transistor S1 achieved according to an exemplaryembodiment the present invention. Therefore, the components and measuresneeded to eliminate or minimize this electromagnetic pollution (EMP) arenecessary to a much smaller extent, which contributes to a considerableimprovement with regard to quality and cost.

According to an exemplary embodiment of the present invention, thetransistor is controlled at the gate with a gate resonance control whena MOS-FET transistor is used as switching transistor S1.

FIG. 4 shows schematically a block diagram of a gate resonance controldesigned according to an exemplary embodiment of the present invention.This gate resonance control or controller contains a gate reactance coilL3 upstream from gate G of a MOS-FET transistor S14 which switches DCsupply voltage U_(E) of a voltage source 41. Gate reactance coil L3 isconnected to the positive pole of a control voltage source 34 over thecathode-anode segment of a first diode D2 and a first transistor switchS2 and is also connected to the reference potential over theanode-cathode segment of a second diode D3 and a second transistorswitch S3. Parasitic gate-drain capacitance C_(GD) and parasiticgate-source capacitance C_(GS) are used as capacitances for the resonantcircuit, as shown with dotted lines in FIG. 4. The clock pulse ofturning the two transistor switches S2 and S3 on and off is selected sothat the gate voltage escalates in the desired manner. Drain D ofswitching transistor S14 is connected to the positive pole of voltagesource 41 across a resistor R1, and source S of switching transistor S14is connected directly to the reference potential or the negative pole ofvoltage source 41.

FIG. 4 shows a time diagram of various signals which occur in theswitching operations of the gate resonance control according to FIG. 4.Thus, the two upper diagrams a) and b) show the turn-on phases, labeledas 1, and the turn-off phases, labeled as 0, of the two transistorswitches S2 and S3 plotted over time t, these phases being offset by 90°el. In the third diagram c), gate voltage U_(G), which is plotted overtime t is escalated out of auxiliary voltage U_(H). In the fourth chart,lower diagram d), gate current I_(G). is plotted over time t.

In the following explanation of the operation and functioning of thegate resonance control, the Miller capacitance, parasitic capacitanceC_(GD) between the gate and the drain, is omitted for the sake ofsimplicity.

If switching transistor S1 is to be turned on, first transistor switchS2 is closed briefly, i.e., it is switched from 0 to 1 according to FIG.5a). Auxiliary voltage or driver voltage U_(H) passes through diode D2to gate reactance coil L3, which then forms a resonant circuit togetherwith capacitance C_(GS). If the voltage on gate G was zero volt at thisinstant, a half sine wave is then formed, with gate voltage U_(G)increasing to twice the auxiliary voltage U_(H) in the ideal case. Atthe moment when the maximum voltage is reached and the gate voltagewould actually swing back, diode D2 becomes non-conducting and thusprevents gate voltage U_(G) from dropping. Thus, the gate voltage U_(G)which has been built up is maintained. Then transistor switch S2 canalso be opened, i.e., switched from 1 to 0 according to FIG. 5a). In theexemplary embodiment using bipolar transistors as transistor switch S2and S3, this has the advantage that the charge carriers can beeliminated now and will not interfere with shutdown later.

If switching transistor S1 is to be turned off, the second transistorswitch S3 is closed briefly, i.e., it is switched from 0 to 1 accordingto FIG. 5b). Thus, the negative pole or ground is connected to thecathode of diode D3. The resonant circuit develops again, nowoscillating from the previous gate voltage U_(G) into a negativevoltage, as illustrated in FIG. 5c). On reaching the minimum voltage,the charge is prevented from dropping back again by diode D3, which thenbecomes non-conducting. The negative voltage that has been built up ismaintained. Like transistor switch S2 above, transistor switch S3 cannow be opened again, which brings the same advantages as those describedabove.

If switching transistor S1 is to be turned on again, transistor switchS2 is closed briefly. Auxiliary voltage U_(H) goes over diode D2 to gatereactance coil L3. L3 together with C_(GS) again forms a resonantcircuit. Since the voltage at gate G already has a negative bias at thistime, gate voltage U_(G) swings to a higher level than before. Aprogressively higher gate voltage U_(G) develops over several periods,limited only by parasitic losses.

Due to the intended escalation of gate voltage U_(G) described here, itis possible in an advantageous manner to use a FET transistor asswitching transistor S1, whose threshold voltage is near or even abovethe auxiliary voltage or driver voltage U_(H). One application mayinvolve the use of a FET transistor with a threshold voltage of 7V withan auxiliary voltage or driver voltage U_(H) of 5V. Another advantage isthe more rapid switching operation, because gate current I_(G) at thetime when the threshold voltage is applied to gate G is the decidingfactor for the switching speed and thus also the switching losses.Assuming that transistor switches S2, S3 can carry a certain maximumcurrent, this yields:

with the conventional control, a current curve which assumes its maximumvalue immediately at the start of the switching phase of transistorswitch S2 and then approaches zero exponentially; the threshold voltageis reached at a time when gate current I_(G) amounts to only a fractionof the maximum value, typically about 50%;

with the gate resonance control according to an exemplary embodiment ofto the present invention, a current curve which describes a sinusoidalrise; with this circuit, gate voltage U_(G) reaches its threshold valueprecisely at the point where gate voltage U_(G) is at its highest (curvein FIG. 5d).

Another advantage of the gate resonance control according to anexemplary embodiment of the present invention is obtained through thecurrent source characteristic of gate reactance coil L3. This can now beexplained on the basis of a shutdown case: when switching transistor S1is turned off, the entire load current is disconnected from the sourcein a very short period of time. The parasitic inductances present in thesource path, e.g., from the bond wire and the layout, induce acorrespondingly high induction voltage due to this high current jump. Ifthe control circuit had voltage characteristics, as is the case withconventional controls, the induced voltage would be added to theexternal gate-source voltage on the semiconductor chip and thus wouldactivate the FET transistor. This would then ultimately result in aslow-down of the shutdown flank and thus to a greater power loss.However, since a current-loaded inductance is in the gate line accordingto an exemplary embodiment of the present invention, this effect is notmanifested. This inductance in turn counteracts the change in currentand in doing so induces a corresponding voltage which compensates forthe voltage induced in the source line.

The influence of Miller capacitance C_(GD) will now be explained. Thiscapacitance prevents the oscillation process because it has a negativefeedback effect. At the moment when gate voltage U_(G) reaches thethreshold voltage of switching transistor S1 in the oscillation process,its drain voltage drops from the previous value to zero, becauseultimately it is turned on. This negative voltage flank is linked togate G over Miller capacitance C_(GD) and at that moment it counteractsthe charge buildup of gate G. If the product of the drain cut-offvoltage applied previously and the Miller capacitance C_(GD) exceeds acertain limit value, then the opposite effect becomes so great that theescalation of gate voltage U_(G) to progressively higher values nolonger functions.

It should be pointed out here that with the MOS-FET transistorsavailable today, the above-mentioned product is close to the limitvalue. Therefore, from the point of view of dimensioning with robustparameters, the actually allowed cut-off voltage of the MOS-FETtransistor cannot be fully utilized with this type of circuit. Theembodiment according to an exemplary embodiment of the present inventiondescribed below creates a remedy of this situation.

FIG. 6 shows schematically in a block diagram the circuit of thequasi-resonant DC-DC converter designed according to an exemplaryembodiment of the present invention, preferably switching at zerovoltage, together with the gate resonance control designed according toan exemplary embodiment of the present invention. The quasi-resonantconverter corresponds exactly to the circuit illustrated in FIG. 1except that auxiliary voltage source 3 connected to gate G of switchingtransistor S1 is connected through the gate resonance control orcontroller in FIG. 4 to gate G of the switching transistor which islabeled there as S14. The circuit composed according to an exemplaryembodiment of the present invention in this embodiment thus combines thequasi-resonant converter designed according to according to an exemplaryembodiment of the present invention as shown in FIG. 1 with the gateresonance control according to an exemplary embodiment of the presentinvention as shown in FIG. 4. The quasi-resonant converter has thespecial advantage that the drain voltage does not increase immediatelywhen the MOS-FET transistor used as switching transistor S1 is turnedoff, in particular not during the switching operation, but instead it isslowed down by the resonant elements. Thus, since only a very lowdrain-source voltage occurs at the FET transistor during the switchingoperation, the Miller capacitance C_(GD) no longer causes interference.Because of the advantageous mutual support and supplementation, the gateresonance control functions especially effectively. Only after theactual switching operation of the FET transistor does the drain-sourcevoltage increase. Although Miller capacitance C_(GD) then takes effect,it has a negative influence only on the value of gate voltage U_(G) butnot on the switching operation itself.

This exemplary embodiment of the present invention reduces the controllosses due to the functioning of the specially designed gate resonancecontrol and minimizes switching losses due to the quasi-resonantconverter. The power loss of the DC-DC converter is thus determinedessentially only by the flux losses in the conducting phase of switchingtransistor S1. Thus, the voltage transformer achieves a very highefficiency. Due to the lower heat loss, a smaller heat sink is requiredaccordingly at the same ambient temperature specifications, bringing acost advantage due to less stringent requirements of the controllerdesign.

This exemplary embodiment of the present invention also makes itpossible for the supply voltage to the driver stage, i.e., auxiliaryvoltage U_(H), to be smaller than the gate threshold voltage ofswitching transistor S1. Due to the gate resonance control designedaccording to an exemplary embodiment of to the present invention, avoltage rise is achieved at the gate, so that even non-logic-level FETtransistors of 5V or more can be controlled.

This exemplary embodiment of the present invention also includes agreatly improved performance with respect to electromagnetic pollution.Since switching transistor S1 can be turned on and off with virtually noloss, a much smaller amount of energy is given off as interference overthe lines and through the air in comparison with a conventionalconverter. This reduces the need for measures such as electromagneticfilters and shields which are otherwise necessary to comply with bothstatutory limits and customer demands, thus reducing costs accordinglywhile also increasing quality.

As explained elsewhere, it is possible with suitable dimensioning to usethe leakage inductance of transformer 2 as the inductive resonanceelement of the series resonant circuit with capacitance C1 instead of adiscrete inductance L1. When using a MOS-PET transistor as switchingtransistor S1, essentially the parasitic output capacitance of thetransistor is suitable as a capacitive resonant element. To narrow thecapacitance tolerance band, should that be necessary, a discretecapacitor such as that shown as C1 may be connected in parallel to thisoutput capacitance of the transistor.

The exemplary embodiment of the present invention thus make available inan advantageous manner a much more effective DC-DC converter, anadvantageous gate resonance control and a very low-loss combination ofthe two elements.

What is claimed is:
 1. A DC-DC voltage converter comprising: an inductance arrangement; a reactance coil, wherein: the reactance coil includes a primary winding, a secondary winding and a connecting tap between the primary winding and the secondary winding; the reactance coil is connected as a transformer to have a transformation ratio; and a DC supply voltage is supplied to the primary winding of the reactance coil over the inductance arrangement; a controllable switching transistor arrangement for turning on and off the DC supply voltage, wherein a contact gap of the controllable switching transistor arrangement is set at a reference potential at the connecting tap; an output capacitor, wherein an output voltage for a load is applicable across the output capacitor; a diode having an anode-cathode segment, wherein the anode-cathode segment of the diode and the output capacitor is set at the reference potential and is in series with the secondary winding of the reactance coil; and a capacitance arrangement arranged in parallel with the contact gap of the controllable switching transistor arrangement so that a series resonant circuit, which is operative in a turn-on phase and a turn-off phase of the controllable switching transistor arrangement, is provided by the inductance arrangement and the capacitance arrangement.
 2. The DC-DC converter of claim 1, wherein the controllable switching transistor arrangement is switched to a conducting state when a voltage applied to a conducting segment of the controllable switching transistor arrangement is approximately zero.
 3. The DC-DC converter of claim 2, further comprising, a circuit arrangement for detecting a voltage applied to the conducting segment of the controllable switching transistor arrangement and for detecting zero crossings.
 4. The DC-DC converter of claim 1, wherein the controllable switching transistor arrangement includes a MOS-FET transistor.
 5. The DC-DC converter of claim 1, wherein the inductance arrangement, connected upstream from the primary winding, includes at least one of a discrete inductance arrangement and a leakage inductance of the reactance coil, the reactance coil having a coupling factor.
 6. The DC-DC converter of claim 1, wherein the capacitance arrangement, parallel to the contact gap of the controllable switching transistor arrangement, is provided by at least one of a discrete capacitance arrangement and a parasitic output capacitance of the controllable switching transistor arrangement.
 7. The DC-DC converter of claim 4, further comprising a gate resonance control arrangement, wherein a gate of the gate resonance control arrangement is used to control the MOS-FET transistor.
 8. A gate resonance control arrangement for a DC-DC voltage converter, which comprises: a gate reactance coil coupled upstream from a gate of the MOS-FET transistor, the MOS-FET transistor switching the DC supply voltage; a first diode having a cathode-anode segment; a first transistor switch; a second diode having a anode-cathode segment; a second transistor switch; the gate reactance coil being connectable to a control voltage source across the cathode-anode segment of the first diode and the first transistor switch, and also being connectable to a reference potential across the anode-cathode segment of the second diode and the second transistor switch; wherein: the capacitance arrangement for the series resonant circuit includes at least one of a parasitic gate drain capacitance and a parasitic gate source capacitance; and a clock pulse for switching on and off the first transistor switch and the second transistor switch is selected so that a gate voltage is escalated as desired.
 9. The gate resonance control arrangement of claim 8, wherein the first transistor switch and the second transistor switch each include a bipolar transistor.
 10. The DC-DC converter of claim 8, wherein the gate resonance control arrangement controls the MOS-FET transistor to switch the DC supply voltage. 